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NM9805
PCI + 1284 Printer Port
Features * Single 5V operation * Low power * PCI compatible 1284 printer port * Multi-mode compatible controller (SPP, PS2, EPP, ECP) * Fast data rates up to 1.5 Mbytes/s (parallel port) * 16-byte FIFO (parallel) * Re-map function for legacy ports * Microsoft Compatible * Software programmable mode selects * 128-pin QFP package Applications * Printer server * Portable backup units * Printer interface * Add-on I/O cards Application Notes * AN-9805
General Description The NM9805 is a 1284 parallel port controller with PCI bus interface. NM9805 fully supports the existing Centronics printer interface as well as PS/2, EPP, and ECP modes. The NM9805 is ideally suited for PC applications, such as high speed parallel ports. The NM9805 is available in a 128-pin QFP package. It is fabricated using an advanced submicron CMOS process to achieve low drain power and high-speed requirements.
Ordering Information Commercial Grade NM9805CV 128-QFP 0 C to +70 C
MosChip Semiconductor 3335 Kifer Rd, Santa Clara, CA 95051 Tel (408) 737-7141 Fax (408) 737-7708
NM9805
PCI + 1284 Printer Port
NM9805 Block Diagram
CLK nRESET AD0 - AD31 nFRAME, nIRDY nLOCK, IDSEL, nTRDY, nSTOP, nDEVSEL, nPARR,nSERR nC/BE0, nC/BE1, nC/BE3, nC/BE4
P C I I N T E R F A C E
P C I
PD0 - PD7
B R I D G E
1284 Parallel Port
FAULT, SLCT, PE nACK, nBUSY nSTROBE, nAUTOFDX INIT, nSLCTIN
nINTA
PCI Clk
EEprom Interface
EE-CLK
EE-CS
EE-DO
Page 2
EE-EN
EE-DI
Rev. 1.1
NM9805
PCI + 1284 Printer Port
128-Pin QFP Package
nRESET
EE-CLK
EE-DO
EE-EN
EE-CS
nINTA
EE-DI
AD29 128
AD30 127
AD31 126
GND
GND 125
GND
VCC
VCC
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C. 124
CLK 122
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
VCC AD28 AD27 AD26 AD25 AD24 GND nC/BE3 IDSEL VCC AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 VCC GND GND nC/BE2 nFRAME nIRDY nTRDY nDEVSEL nSTOP nLOCK nPERR nSERR PAR nC/BE1 GND AD15 AD14 AD13 AD12 AD11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VCC 40 AD10 41 AD9 42 AD8 43 nC/BE0 44 GND 45 GND 46 AD7 47 AD6 48 AD5 49 AD4 50 AD3 51 AD2 52 AD1 53 AD0 54 VCC 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
N.C. N.C. N.C. GND PD7 PD6 PD5 PD4 GND PD3 PD2 PD1 PD0 VCC GND PE nACK nBUSY SLCT FAULT VCC nSTROBE nAUTOFDX INIT nSLCTIN GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VCC N.C.
NM9805CV
N.C. N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C.
Rev. 1.1
Page 3
NM9805
PCI + 1284 Printer Port
Pin Name CLK nRESET 128 122 121 Type I I Description 33 MHz PCI system clock input. PCI system reset (active low). Resets all internal register, sequencers, and signals to a consistent state. During reset condition AD31-0, nSER are threestated. Multiplexed PCI address/data bus. A bus transaction consists of an address phase followed by one or more data phases. During the address phase, AD310 contain a physical address. Write data is stable and valid when nIRDY and nTRDY are asserted (active). See AD31-29 description. See AD31-29 description. See AD31-29 description. See AD31-29 description. See AD31-29 description. Frame is driven by the current master to indicate the beginning and duration of an access. nFRAME is asserted to indicate a bus transaction is beginning. While nFRAME is active, data transfer continues. Initiator Ready. During a write, nIRDY asserted indicates that the initiator is driving valid data onto the data bus. During a read, nIRDY asserted indicates that the initiator is ready to accept data from the NM9805. Target Ready (three-state). It is asserted when NM9805 is ready to complete the current data phase. NM9805 asserts nSTOP to indicate that it wishes the initiator to stop the transaction in process on the current data phase. Lock indicates an atomic operation that may require multiple transactions to complete. Initialization Device Select. It is used as a chip select during configuration read and write transactions. Device Select (three-state). NM9805 asserts nDEVSEL when the NM9805 has decoded its address. Parity Error (three-state). Is used to report parity errors during all PCI trans-
AD31-29 126-128
I/O
AD28-24 AD23-16 AD15-11 AD10-8 AD7-0 nFRAME
2-6 11-18 34-38 40-42 46-53 23
I/O I/O I/O I/O I/O I
nIRDY
24
I
nTRDY
25
O
nSTOP
27
O
nLOCK
28
I
IDSEL
9
I
nDEVSEL
26
O
nPERR
29
O
Page 4
Rev. 1.1
NM9805
PCI + 1284 Printer Port
Pin Name 128 Type Description actions except a special cycle. The minimum duration of nPERR is one clock cycle. nSERR 30 O System Error (open drain). This pin goes low when address parity errors are detected. Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable and valid one clock after the address phase. For data phase, PAR is stable and valid one clock after either nIRDY is asserted on a write transaction, or nTRDY is asserted on a read transaction. Bus Command and Byte Enable. During the address phase of a transaction, nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used as byte enables. nC/BE3 applies to byte "3". Bus Command and Byte Enable. During the address phase of a transaction, nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used as byte enables. nC/BE2 applies to byte "2". Bus Command and Byte Enable. During the address phase of a transaction, nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used as byte enables. nC/BE1 applies to byte "1". Bus Command and Byte Enable. During the address phase of a transaction, nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used as byte enables. nC/BE0 applies to byte "0". PCI active low interrupt output (open-drain). This signal goes low (active) when an interrupt condition occurs. External EEprom chip select (active high). After power on reset, NM9805 reads the EE-Prom and loads the read-only configuration registers sequentially from the first 64 bytes in the EE-Prom. External EEprom clock. External EEprom data input. External EEprom data output. Enable/Disable external EEprom (active high, internal pull-up). External EEprom can be disabled when this pin is tied to GND or pulled low. When external EEprom is disabled, the default values for NM9805 will be loaded into PCI configuration register.
PAR
31
I/O
nC/BE3
8
I
nC/BE2
22
I
nC/BE1
32
I
nC/BE0
43
I
nINTA
120
O
EE-CS
115
O
EE-CLK EE-DI EE-DO EE-EN
116 118 117 123
O I O I
Rev. 1.1
Page 5
NM9805
PCI + 1284 Printer Port
Pin Name SLCT 128 84 Type I Description Peripheral/printer selected (internal pull-up). This pin is set to high by peripheral/printer when it is selected. Paper empty (internal pull-up). This pin is set to high by peripheral/printer when printer paper is empty. Peripheral/printer busy (internal pull-up). This pin is set to high by peripheral/ printer when printer or peripheral is not ready to accept data. Peripheral/printer data acknowledge (internal pull-up). This pin is set to low by peripheral/printer to indicate a successful data transfer has taken place. During SPP mode when interrupt is enabled, nINTA pin follows the nACK input pin state. Peripheral/printer data error (internal pull-up). This pin is set to low by peripheral/printer during error condition. Peripheral/printer data strobe (open drain, active low). On the rising edge of the nSTROBE, data is latched into printer port. Peripheral/printer auto feed (open-drain, active low). Continuous autofed paper is selected when this pin is set to low. Initialize the Peripheral/printer (open drain, active low). When set to low, peripheral/printer starts it's initialization routine. Peripheral/printer select (open-drain, active low). Selects the peripheral/printer when it is set to low. Peripheral/printer data ports. Peripheral/printer data ports. Power and signal ground.
PE
87
I
nBUSY
85
I
nACK
86
I
nFAULT
83
I
nSTROBE
81
I/O
nAUTOFDX 80
I/O
nINIT
79
I/O
nSLCTIN
78
I/O
PD7-PD4 PD3-PD0 GND
98-95 93-90 7,20,21, 33,44,45, 60,77,88, 94,99,108 119,125
I/O I/O Pwr
VCC
1,10,19, 39,54,66, 82,89,104, 114
Pwr
5V supply.
Page 6
Rev. 1.1
NM9805
PCI + 1284 Printer Port
PCI bus operation: The execution of PCI bus transaction takes place in broadly five stages: address phase; transaction claiming; data phase(s); final data transfer; and transaction completion. Address phase: Every PCI transaction starts off with an address phase, one PCI clock period in duration. During address phase the initiator (also known as current bus master) identifies the target device (via the address) and type of transaction (via the command). The initiator drives the 32-bit address onto 32-bit address/data bus and 4-bit command onto 4-bit command/byte enable bus. The initiator also asserts the nFRAME signal during the same clock cycle to indicate the presence of valid address and transaction type on those buses. The initiator supplies start address and command type for one PCI clock cycle. The target, NM9805, generates the subsequent sequential addresses for burst transfers. The address/ data bus becomes data bus and command/byte enable bus becomes byte enable bus for the remainder of the clock cycles of that transaction. The target (NM9805) latches the address and command type on the next rising edge of PCI clock, as do all the devices on that PCI bus. The target (NM9805) decodes the address and determines whether it is being addressed, and decodes the command to determine the type of transaction. Claiming the transaction: When NM9805 determines that it is the target of a transaction, it claims the transaction by asserting nDEVSEL. Data phase(s): The data phase of a transaction is the period during which a data object is transferred between the initiator and the target (NM9805). The number of data bytes to be transferred during a data phase is determined by the number of command/byte enable signals that are asserted by the initiator during the data phase. Each data phase is at least one PCI clock period in duration. Both initiator and target must indicate that they are ready to complete a data phase. If not, the data phase is extended by a wait state of one clock period in duration. The initiator and the target indicate this by asserting nIRDY and nTRDY respectively and the data transfer is completed at the rising edge of the next PCI clock. Transaction duration: The initiator, as stated earlier, gives only start address during address phase but does not tell the number of data transfers in a burst transfer transaction. However, the initiator indicates the completion of data transfer of a transaction by asserting nIRDY and de-asserting nFRAME during the last data transfer phase. The transaction, however, does not complete until the target has also asserted the nTRDY signal and the last data transfer takes place. At this point the nTRDY and nDEVSEL are de-asserted by the target. Transaction completion: When all of nIRDY, nTRDY, nDEVSEL, and nFRAME are in inactive state (high state), the bus is in idle state. The bus is ready to be claimed by another bus master.
Internal address select configuration
I/O Address Function YX0-YX07 WX00 WX01 WX02 Standard Printer Printer Configuration Register A Printer Configuration Register B Printer ECR Register
Rev. 1.1
Page 7
NM9805
PCI + 1284 Printer Port
NM9805 configuration space register map
AD 31-23
AD 22-16
AD 15-8
AD 7-0
Addr 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H
Device ID (9805) Status Class Code (070102) BIST Header Type
Vendor ID (9710) Command Revision ID (01) Latency Timer Cache Size (08)
I/O (Y)Base Address I/O (W)Base Address Reserved Reserved Reserved Reserved Reserved Subsystem ID Reserved Reserved Reserved Max Latency (00) Min Grant (00) Interrupt Pin (01) Interrupt Line Subsystem Vendor ID
2CH 30H 34H 38H 3CH
Page 8
Rev. 1.1
NM9805
PCI + 1284 Printer Port
Printer Register Table
Ex A2 A1 A0 Y0 Y0 0 0 0 1 REGISTER DPR DSR D7 PD7 nBUSY D6 PD6 nACK D5 PD5 PE D4 PD4 SLCT D3 PD3 FAULT D2 PD2 INT state INIT ADD-2 D1 PD1 "0" D0 PD0 EPP TIMEOUT
Y0 Y0
1 1
0 1
DCR EPP Address EPP data EPP data EPP data EPP data C-FIFO CONF-A CONF-B
"0" ADD-7
"0" ADD-6
DIR ADD-5
INTA ADD-4
nSLCTIN ADD-3
nAUTOFD nSTROBE ADD-1 ADD-0
Y1
0
0
DAT-7
DAT-6
DAT-5
DAT-4
DAT-3
DAT-2
DAT-1
DAT-0
Y1
0
1
DAT-15
DAT-14
DAT-13
DAT-12
DAT-11
DAT-10
DAT-9
DAT-8
Y1
1
0
DAT-23
DAT-22
DAT-21
DAT-20
DAT-19
DAT-18
DAT-17
DAT-16
Y1
1
1
DAT-31
DAT-30
DAT-29
DAT-28
DAT-27
DAT-26
DAT-25
DAT-24
W0 W0 W0
0 0 0
0 0 1
CDAT-7 "1" "0"
CDAT-6 "0" INT Pin MODE select
CDAT-5 "0" "0"
CDAT-4 "1" "0"
CDAT-3 "0" "0"
CDAT-2 "1" "0"
CDAT-1 "0" "0"
CDAT-0 "0" "0"
W0
1
0
ECR
ErrIntrEn enable
"0"
Service Int
FIFO full
FIFO empty
Y: Internal standard printer chip select W: Internal printer configuration register chip select
Rev. 1.1
Page 9
NM9805
PCI + 1284 Printer Port
Data Register Data register is cleared at initialization by RESET. During a write operation, the data register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered and output onto the PD7-PD0 ports. During a read operation PD7-PD0 ports are buffered and output to the host CPU on the falling edge of the nIOR input. Device Status Register The contents of this register are latched for the duration of the nIOR cycle. The bits of the status port are defined as follows. DSR Bit-0: 0 = Normal. 1 = 10s timeout (EPP mode only). Cleared by writing 1 into DSR register or consecutive reads (after the first read) always returns to "0". DSR Bit-1: Not used, set to "0". DSR Bit-2: 0 = nACK input pin is at low state (INT follows the nACK pin) when SPP mode is selected. Normal (no interrupt) when PS/2 mode is selected. 1 = Normal (no interrupt). In standard mode operation, INT is active (interrupt is generated on the rising edge of the nACK). It is cleared when DSR is read. DSR Bit-3: 0 = Printer reports error condition. 1 = Normal operation. DSR Bit-4: 0 = Printer is off line. 1 = Printer is on line. DSR Bit-5: 0 = Normal operation 1 = Paper end/empty is detected DSR Bit-6: 0 = State of the nACK pin (ACK = low). 1 = State of the nACK pin (ACK = high). DSR Bit-7: 0 = nBUSY pin is high, printer is not ready to take data. 1 = nBUSY pin is low, printer is read to take data. Device Control Register DCR Bit-0: 0 = Sets the nSTROBE pin to high. 1 = Sets the nSTROBE pin to low. PD7-PD0 data are latched into printer DCR Bit-1: 0 = Sets the nAUTOFD pin to high. Printer generates auto line feed after each line is printed. 1 = Sets the nAUTOFD pin to low. No auto feed function. DCR Bit-2: 0 = Sets the INIT pin to high. 1 = Sets the INIT pin to low. Peripheral/printer starts it's initialization routine. DCR Bit-3: 0 = Sets the nSLCTIN pin to high. Selects the printer. 1 = Sets the nSLCTIN pin to low. Printer is not selected. DCR Bit-4: 0 = Disables Printer interrupt function. nACK pin has no effect on the INT pin. 1 = Enables Printer interrupt function. The INT follows the nACK input pin during standard mode, latches high on the rising edge of the nACK, when PS/2 mode is selected. DCR Bit-5: 0 = PD7-PD0 pins are out put mode. 1 = PD7-PD0 pins are input mode. DCR Bits 7-6: Not used, set to "0". Config-A Register Configuration A register (read only). Reading this register returns 10010100. Writing to this register has no effect and the data is ignored.
Page 10
Rev. 1.1
NM9805
PCI + 1284 Printer Port
Config-B Register Configuration B register. This register allows software to control the selecting of interrupts. A read-write implementation implies a "software-configurable" device. Reading this register returns the configured interrupt and interrupt pin state. If a value is not set to 000 (the jumper-default) then it is assumed that the value in the register is correct and software will use the default interrupt. Config-B Bit-7: Not used, set to "0". Config-B Bit-6: 0 = Configured printer interrupt pin is low. 1 = Configured printer interrupt pin is high. Config-B Bit 7-0: Interrupt pin select register. Mode "000" SPP/Centronics/Compatible Mode Forward direction only. The direction bit is forced to "0" and PD7-PD0 are set to output direction. The NM9805 is under software control. This mode defines the protocol used by most PCs to transfer data to a printer. It is commonly called the Centronics mode and is the method utilized with the standard parallel port. Data is placed on the PD7-PD0 ports, the printer status is checked via DSR register. If no error condition is flagged and printer is not busy, software toggles the nSTROBE pin to latch the PD7-PD0 data into printer. This operating cycle continues when printer/peripheral issues data acknowledge signal (pulses the ACK and nBUSY pin). Nibble Mode The nibble mode is the most common way to get reverse channel data from a printer or peripheral. This mode is usually combined with the Centronics mode or a proprietary forward channel mode to create a bi-directional channel. In this mode printer status bits are used as nibble bits. Bits order for nibble mode
PINS DATA Bits Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Extended Control Register (ECR) This register controls the mode selection and DMA operation.
Bit-7 0 0 0 0 1 1 1 1
Bit-6 0 0 1 1 0 0 1 1
Bit-5 0 1 0 1 0 1 0 1
Operating Mode SPP PS/2 PPF (FIFO mode) ECP EPP Not used FIFO test Config A/B enable
nBUSY PE SLCT nFAULT nBUSY PE SLCT nFAULT
Mode changes After hardware reset, PS/2 mode is selected as default mode. It is required to select mode 000 or 001 between any other mode configuration.
Mode "001" PS/2, Byte Mode The byte mode protocol is used to transfer bi-directional data via PD7-PD0 ports without FIFO utilization. The direction of the port is controlled with DIR bit in DCR register. PS/2-byte use SPP protocol for data transfer. DCR Bit-5: 0 = PD7-PD0 pins are out put mode. 1 = PD7-PD0 pins are input mode.
Rev. 1.1
Page 11
NM9805
PCI + 1284 Printer Port
Mode "010" FIFO Output Mode In this mode, bytes written to the FIFO are transmitted automatically using the SPP/Centronics standard protocol. Mode "011" Extended Capability Port "ECP" Mode The ECP provides an advanced mode for communication with printer or peripherals. Like EPP protocol, ECP provides 16-byte FIFO for a high performance bi-directional communication path between the host adapter and the peripheral. The ECP protocol provides the following cycle types in both the forward and reverse directions: * Data cycle * Command cycles * Run-Length counts (RLE) * Channel address The RLE feature enables real time data compression that can achieve compression ratios up to 64:1. This is particularly useful for printers and peripherals that are transferring large raster images that have large strings of identical data. In order for the RLE mode to be enabled, both the host and peripheral must support it. Channel addressing is intended to address multiple logical devices within a single physical device, like modem/ FAX/printer in one physical package. Mode "100" Enhanced Parallel Port "EPP" Mode In EPP mode, nSLCTIN (address strobe) and nAUTOFD (data strobe) are automatically generated while nSTROBE indicates a write or read cycle. Additional I/ O addresses are defined for data and address access and when these locations are used, handshaking is performed automatically by NM9805. Mode "110" FIFO Test Mode In this mode, the FIFO can be written and read in any direction, but no data will be transmitted on the PD7PD0 ports. Whatever data is in the FIFO may be displayed on the PD7-PD0 ports. ECR Bit-4: Error Interrupt Enable. 0 = Enable nFAULT interrupt. nFAULT pin is used as source of interrupt. 1 = Disable nFAULT interrupt (nACK is used as source of interrupt). ECR Bit-3: 0 = normal operating mode. ECR Bit-2: 1 = Disables service interrupt. 0 = Enables one of the following 3 cases of interrupts. One of the 3 service interrupts has occurred. Service interrupt bit will be set to a "1" by hardware. Writing this bit to a "1" will not cause an interrupt. Port Direction (DCR Bit-5 = 0). This bit will be set to "1" whenever there are write interrupt thresholds (4 characters) or more bytes free in the FIFO. The NM9805 generates interrupt when this condition is occurred and service interrupt is cleared to "0". Port Direction (DCR Bit-5 = 1). This bit will be set to "1" whenever there are read interrupt thresholds (12 characters) or more bytes to be read from the FIFO. The NM9805 generates interrupt when this condition is occurred and service interrupt is cleared to "0". ECR Bit-1: 0 = One or more empty locations in FIFO is available. 1 = FIFO full. ECR Bit-0: 0 = One or more data in FIFO. 1 = FIFO empty.
Page 12
Rev. 1.1
NM9805
PCI + 1284 Printer Port
Master rest conditions
Register DPR DSR DCR EPP C-FIFO CONF-A CONF-B ECR
BIT-7 X 0 0 0 0 1 0 0
BIT-6 X 1 0 0 0 0 X 0
BIT-5 X 1 0 0 0 0 0 0
BIT-4 X 1 0 0 0 1 0 0
BIT-3 X 1 0 0 0 0 0 0
BIT-2 X 0 0 0 0 1 0 0
BIT-1 X 0 0 0 0 0 0 0
BIT-0 X 0 0 0 0 0 0 1
Rev. 1.1
Page 13
NM9805
PCI + 1284 Printer Port
Absolute Maximum Ratings Supply Range Voltage at any pin Operating Temperature Storage Temperature Package Dissipation ESD Latch up 7 Volts GND - 0.3 to VCC +0.3 -45 C to 90 C -65 C to 150 C 500 mW 2000 Volts 220 mA
DC Electrical Specification T = 0 C to 70 C, VCC = 5V 10% unless otherwise specified.
Symbol
Parameter Min
5V Max 0.8
Unit
Condition
Vil Vih Vt-
Input Low voltage Input High voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input low current Input high current Three state leakage current Input capacitance Output capacitance Operating current
-0.3 2.0 1.10
V V V
Vt+
1.87
V
Vol Voh Iil Iih Ioz Cin Cout Icc
0.4 3.5 1 1 10 3 3 5 5 60
V C A A A pF pF mA
Iol=4 mA Ioh=4 mA
No load
Revision 1.1
Notes Ordering information changed
Date 7/02
Page 14
Rev. 1.1
NM9805
PCI + 1284 Printer Port
128-Pin QFP (14X20) Package
HE E
128 1
103 102
38 39 64
65 D HD
e
b
A2 A1
c
L
SYMBOL MIN A1 A2 b c e L HD D HE E 0.10 2.73 0.17 0.09
MILLIMETERS MAX 0.30 2.97 0.27 0.20 0.50 TYP 0.70 23.00 19.90 17.00 13.90 1.03 23.40 20.10 17.40 14.10 0.029 0.906 0.783 0.669 0.547 MIN 0.004 0.107 0.007 0.004
INCHES MAX 0.012 0.117 0.011 0.008 0.020 TYP 0.041 0.921 0.791 0.685 0.555
Rev. 1.1
Page 15
NM9805
PCI + 1284 Printer Port
IMPORTANT NOTICE
MosChip Semiconductor Technology, LTD products are not authorized for use as critical components in life support devices or systems. Life support devices are applications that may involve potential risks of death, personal injury or severe property or environmental damages. These critical components are semiconductor products whose failure to perform can be reasonably expected to cause the failure of the life support systems or device, or to adversely impact its effectiveness or safety. The use of MosChip Semiconductor Technology LTD's products in such devices or systems is done so fully at the customer risk and liability. As in all designs and applications it is recommended that the customer apply sufficient safeguards and guard bands in both the design and operating parameters. MosChip Semiconductor Technology LTD assumes no liability for customer's applications assistance or for any customer's product design(s) that use MosChip Semiconductor Technology, LTD's products. MosChip Semiconductor Technology, LTD warrants the performance of its products to the current specifications in effect at the time of sale per MosChip Semiconductor Technology, LTD standard limited warranty. MosChip Semiconductor Technology, LTD imposes testing and quality control processes that it deems necessary to support this warranty. The customer should be aware that not all parameters are 100% tested for each device. Sufficient testing is done to ensure product reliability in accordance with MosChip Semiconductor Technology LTD's warranty. MosChip Semiconductor Technology, LTD believes the information in this document to be accurate and reliable but assumes no responsibility for any errors or omissions that may have occurred in its generation or printing. The information contained herein is subject to change without notice and no responsibility is assumed by MosChip Semiconductor Technology, LTD to update or keep current the information contained in this document, nor for its use or for infringement of patent or other rights of third parties. MosChip Semiconductor Technology, LTD does not warrant or represent that any license, either expressed or implied, is granted to the user.
Printed July 31, 2002
Page 16
Rev. 1.1

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